Matthew Kopala

Matthew Kopala

mkopala@freeshell.org

OBJECTIVE Work? Yes, I suppose I will look for that sometime. If you want to me to work remote while I'm traveling, that could work ...

TRAVEL
10/02 - Present
Travel through Peru, Bolivia, Brazil, Paraguay, Uruguay, Argentina, Chile, New Zealand, Australia, Papua New Guinea, Indonesia, and East Timor. Plans to continue to Singapore, Malaysia, Thailand, Philippines, Taiwan, Vietnam, Laos, Cambodia, India, Sri Lanka, Nepal, Myanmar, China, Mongolia, and Korea in the next year and a half.

RELEVENT
EXPERIENCE
8/00 - 7/02
ADVANCED MICRO DEVICES Austin, TX
Product Development Engineer I
Logic implementation using standard cells of the RTL description of the AMD K8 Floating Point Adder design module. Optimization of logic for timing. Formal verification and debug of logic using Chrysalis. Placement of standard cell logic for optimal timing. Speedpath analysis & fixes using Synopsys PrimeTime, edgerate & fanout reduction, hold timing fixes, minimal logic implemenation using DFT tools. Improvements to placement to decrease route congestion, improve routes, and fix crosstalk problems
Shared responsibility for managing floorplan and connectivity database for Floating Point (FP) design modules. Added and managed buffer chains for signals traveling across the chip and crossing design module boundaries. Optimization of the chains for timing and minimal route congestion.
Designed to build a full-chip level database from several design sub-modules, create a netlist for the design for use with PrimeTime, stitch parasitics together for the modules, run timing and generate critical path reports and other custom timing reports. Created scripts to parse the reports by design module and present the data in an easily-accessibly format using a HTML web page. This flow allowed for a drastic improvement in turn-around time for full-chip level timing information over the pre-existing full-chip build process. It also made it fast and simple to view timing status through the use of web pages, as well as quickly determine the optimal fix for timing problems.
Added several procedures to the proprietary database of TCL procedures used to gather timing information from Sysnopsys PrimeTime. Fixed bugs and enhanced existing code used in full chip and design module timing runs. Acted as one of a handful of PrimeTime experst for the implementation and CAD teams.
Responsible for routing and optimization of a route-level module (RLM) comprised of several Floating Point sub-level modules (SLMs). Create preroutes for timing critical, crosstalk susceptible signals, and signals in congested areas. Conducted several route experiments with different metal layer costs and other router configuration variables in both global and final routing to determine the best choices for optimal timing results. Pioneered and tested a method of routing a user-defined list of critical nets first with adjusted costs. Shared results of experiments with design team. Added the route-first ability to the flow used by the design team.
Gained thorough understanding of the design flow and scripts used during the flow. Used this expertise to solve problems whith the flow or tools that I encountered as and end-user. Assisted the CAD team in investigating and solving problems seen by other users. Made changes, improvements, and optimizations to the design flow. Provided assistance and expertise to the design team and other CAD team members as needed. Updated CAD FAQ web document with information about changes.
Designed a flow for combining all of the route-level module (RLM) designs into a full-chip database. Worked with another engineer in adding functionality to create the netlist, stitch the parasitics together, and run full-chip timing on the entire chip. Created scripts to generate a HTML web page summary of the edge rate violations across the chip. This flow was used to gather the timing information used for tapeout signoff.
Designed a flow to collect and stitch SPF parasitics from various RLMs into a new SPF file so that crosstalk could be properly analyzed on signals that cross RLM boundaries. Used Perl for development and carefully engineered the flow so that the task would be feasible in terms of memory and time.
Updated and maintained the Floating Point Implementation web page. Updated list of team members, added links to design scoreboard, floorplan, timing data, API documentation, and other useful pages. Created pages with up-to-date data on SLM and RLM progress.

5/99 - 8/99
8/98 - 12/98
ADVANCED MICRO DEVICES Austin, TX
Co-op Engineer
Verify design of PC chipset south bridge. Work with block designers and other verification engineers to develop simulation environment for verifying functionality of Verilog RTL design. Write, run and debug Verilog tests, write and modify Verilog models. Write and modify Perl scripts used within environment. Spice analysis of CMOS standard library circuits.

5/98 - 8/98

THE UNIVERSITY OF ARIZONA Tucson, AZ
Research Assistant
Design part of a GUI interface for National Science Foundation funded project to design a computer driven system to aid in the analysis of tree ring patterns. Interface created using Tcl/Tk.

8/97 - 3/98

THREE-FIVE SYSTEMS, INC. Tempe, AZ
MIS Database Designer
Development of database using Microsoft Access 7.0/97 to manage employee and equipment information. Design of database interface to assist MIS personnel in tracking support tasks.

6/97 - 8/97

MIS Systems Specialist
Hardware & Software installation, setup and configuration of PCs and laptops for employees. Troubleshoot, fix problems with Novell NetWare network, user PCs. Configure user accounts on NetWare, VAX/VMS, and UNIX.

SKILLS Computer Skills

UNIX (Linux, Solaris), Windows 98/NT/2000

Perl, C, C++, Tcl/Tk, CVS, RCS, Verilog, Make, HTML

Tools

Synopsys PrimeTime, Chrysalis, Cadence Silicon Ensemble DSM, Simplex Fire & Ice

MathCAD, MicroSim PSpice, MetaSoft Hspice, DAI Signalscan

File Formats

LEF, DEF, DSPF, SPEF, Verilog

Other Skills

Experience with several aspects of microprocessor design, including logic implementation, standard cells, clock grids and buffering, scan chains, placement and routing, parasitics extraction and files, crosstalk analysis, min and max static timing optimization, formal logic verification, dynamic coupling, CAD tools and design methodology.
Experience with design and use of Application Programmer Interfaces (APIs) implemented in C++. Including APIs for netlist, placement, and route information, DEF/LEF, Synopsys libaries, and parasitics information.
Logic gate design (gates, decoders, multiplexers, flip-flops, adders, combinational and sequential circuits, shift registers.

Knowledge of x86 architecture, PCI, ISA, and LPC buses, System Management, USB architecture, cache memory, pipelining, ROM, interrupts, DMA, split transaction bus concepts.

HONORS University of Arizona Honors Program, 1996-2000
College of Engineering and Mines Dean's List, 1997 - 2000
University of Arizona Regents' Scholarship, 1996-2000
Eagle Scout, Boy Scouts of America
William L. Everitt Award for Excellence
University of Arizona ECE Department Outstanding Senior

EDUCATION THE UNIVERSITY OF ARIZONA
Bachelor of Science, Computer Engineering, May 2000
Summa Cum Laude, With Honors, Overall GPA: 3.93/4.00

LANGUAGES English; conversational German, Spanish, Indonesian, PNG Pidgin; some Japanese, Portuguese

CITIZENSHIP United States of America

REFERENCES Available upon request

OBJECTIVE	Work? Yes, I suppose I will look for that sometime. If you want to me to work remote while I'm traveling, that could work ...

TRAVEL 10/02 - Present	Travel through Peru, Bolivia, Brazil, Paraguay, Uruguay, Argentina, Chile, New Zealand, Australia, Papua New Guinea, Indonesia, and East Timor. Plans to continue to Singapore, Malaysia, Thailand, Philippines, Taiwan, Vietnam, Laos, Cambodia, India, Sri Lanka, Nepal, Myanmar, China, Mongolia, and Korea in the next year and a half.

RELEVENT EXPERIENCE 8/00 - 7/02	ADVANCED MICRO DEVICES Austin, TX Product Development Engineer I Logic implementation using standard cells of the RTL description of the AMD K8 Floating Point Adder design module. Optimization of logic for timing. Formal verification and debug of logic using Chrysalis. Placement of standard cell logic for optimal timing. Speedpath analysis & fixes using Synopsys PrimeTime, edgerate & fanout reduction, hold timing fixes, minimal logic implemenation using DFT tools. Improvements to placement to decrease route congestion, improve routes, and fix crosstalk problems Shared responsibility for managing floorplan and connectivity database for Floating Point (FP) design modules. Added and managed buffer chains for signals traveling across the chip and crossing design module boundaries. Optimization of the chains for timing and minimal route congestion. Designed to build a full-chip level database from several design sub-modules, create a netlist for the design for use with PrimeTime, stitch parasitics together for the modules, run timing and generate critical path reports and other custom timing reports. Created scripts to parse the reports by design module and present the data in an easily-accessibly format using a HTML web page. This flow allowed for a drastic improvement in turn-around time for full-chip level timing information over the pre-existing full-chip build process. It also made it fast and simple to view timing status through the use of web pages, as well as quickly determine the optimal fix for timing problems. Added several procedures to the proprietary database of TCL procedures used to gather timing information from Sysnopsys PrimeTime. Fixed bugs and enhanced existing code used in full chip and design module timing runs. Acted as one of a handful of PrimeTime experst for the implementation and CAD teams. Responsible for routing and optimization of a route-level module (RLM) comprised of several Floating Point sub-level modules (SLMs). Create preroutes for timing critical, crosstalk susceptible signals, and signals in congested areas. Conducted several route experiments with different metal layer costs and other router configuration variables in both global and final routing to determine the best choices for optimal timing results. Pioneered and tested a method of routing a user-defined list of critical nets first with adjusted costs. Shared results of experiments with design team. Added the route-first ability to the flow used by the design team. Gained thorough understanding of the design flow and scripts used during the flow. Used this expertise to solve problems whith the flow or tools that I encountered as and end-user. Assisted the CAD team in investigating and solving problems seen by other users. Made changes, improvements, and optimizations to the design flow. Provided assistance and expertise to the design team and other CAD team members as needed. Updated CAD FAQ web document with information about changes. Designed a flow for combining all of the route-level module (RLM) designs into a full-chip database. Worked with another engineer in adding functionality to create the netlist, stitch the parasitics together, and run full-chip timing on the entire chip. Created scripts to generate a HTML web page summary of the edge rate violations across the chip. This flow was used to gather the timing information used for tapeout signoff. Designed a flow to collect and stitch SPF parasitics from various RLMs into a new SPF file so that crosstalk could be properly analyzed on signals that cross RLM boundaries. Used Perl for development and carefully engineered the flow so that the task would be feasible in terms of memory and time. Updated and maintained the Floating Point Implementation web page. Updated list of team members, added links to design scoreboard, floorplan, timing data, API documentation, and other useful pages. Created pages with up-to-date data on SLM and RLM progress.

5/99 - 8/99 8/98 - 12/98	ADVANCED MICRO DEVICES Austin, TX Co-op Engineer Verify design of PC chipset south bridge. Work with block designers and other verification engineers to develop simulation environment for verifying functionality of Verilog RTL design. Write, run and debug Verilog tests, write and modify Verilog models. Write and modify Perl scripts used within environment. Spice analysis of CMOS standard library circuits.

5/98 - 8/98	THE UNIVERSITY OF ARIZONA Tucson, AZ Research Assistant Design part of a GUI interface for National Science Foundation funded project to design a computer driven system to aid in the analysis of tree ring patterns. Interface created using Tcl/Tk.

8/97 - 3/98	THREE-FIVE SYSTEMS, INC. Tempe, AZ MIS Database Designer Development of database using Microsoft Access 7.0/97 to manage employee and equipment information. Design of database interface to assist MIS personnel in tracking support tasks.

6/97 - 8/97	MIS Systems Specialist Hardware & Software installation, setup and configuration of PCs and laptops for employees. Troubleshoot, fix problems with Novell NetWare network, user PCs. Configure user accounts on NetWare, VAX/VMS, and UNIX.

SKILLS	Computer Skills UNIX (Linux, Solaris), Windows 98/NT/2000 Perl, C, C++, Tcl/Tk, CVS, RCS, Verilog, Make, HTML Tools Synopsys PrimeTime, Chrysalis, Cadence Silicon Ensemble DSM, Simplex Fire & Ice MathCAD, MicroSim PSpice, MetaSoft Hspice, DAI Signalscan File Formats LEF, DEF, DSPF, SPEF, Verilog Other Skills Experience with several aspects of microprocessor design, including logic implementation, standard cells, clock grids and buffering, scan chains, placement and routing, parasitics extraction and files, crosstalk analysis, min and max static timing optimization, formal logic verification, dynamic coupling, CAD tools and design methodology. Experience with design and use of Application Programmer Interfaces (APIs) implemented in C++. Including APIs for netlist, placement, and route information, DEF/LEF, Synopsys libaries, and parasitics information. Logic gate design (gates, decoders, multiplexers, flip-flops, adders, combinational and sequential circuits, shift registers. Knowledge of x86 architecture, PCI, ISA, and LPC buses, System Management, USB architecture, cache memory, pipelining, ROM, interrupts, DMA, split transaction bus concepts.

HONORS	University of Arizona Honors Program, 1996-2000 College of Engineering and Mines Dean's List, 1997 - 2000 University of Arizona Regents' Scholarship, 1996-2000 Eagle Scout, Boy Scouts of America William L. Everitt Award for Excellence University of Arizona ECE Department Outstanding Senior

EDUCATION	THE UNIVERSITY OF ARIZONA Bachelor of Science, Computer Engineering, May 2000 Summa Cum Laude, With Honors, Overall GPA: 3.93/4.00

LANGUAGES	English; conversational German, Spanish, Indonesian, PNG Pidgin; some Japanese, Portuguese

CITIZENSHIP	United States of America

REFERENCES	Available upon request